Understanding the Roofline Model 

(continued from previous replies)

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I guess you may have another potential question about why I have used 1 cycle for pipelined access in my calculations. The spec#6 mentions: “*Accessing the cache memory is pipelined and costs 5 cycles.*”

The cost of 5 cycles is again just an example value, and it could be something else. But for the sake of simple explanation, let’s assume a single multiplication (inside the for loop) takes 5 cycles in total, corresponding to each of these steps, each of which takes 1 cycle:


1. Separate mantissa/exponent 2. Multiply mantissas 3. Add exponents 4. Normalize result 5. Put correct sign

But we have a pipeline access, which means all these steps can be interleaved together and we only need 1 cycle to perform these accesses.

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I hope this clears your doubts. Feel free to discuss more on this.

Looks like Hackernoon’s comment feature is a bit buggy. The comments don’t get published immediately; if you click “Reply” multiple times, it posts the same comment multiple times. 

Hi there,

It feels great that the article helped you in understanding the concepts. Thanks for the feedback.

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Regarding your question, I wish to highlight that the specifications for the machine I’ve mentioned are just examples of potential values for the pipelined access. So, the cost of 10 cycles is just a possible value (and it could be something else). The motivation behind the examples was to try to understand the concepts, so it doesn't matter what exactly the value is. 

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If you’re doing roofline modeling yourself, you can get exact values from your processor's Technical Reference Manual (TRM). Another way of getting the values could be using tools like “likwid” and metrics like CPIs and a total number of accesses to calculate these latencies. 

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(continued in the next reply…)

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